`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:13:14 10/22/2012 
// Design Name: 
// Module Name:    ACC_UNIT 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ACC_UNIT #(parameter LOG_CYCLE=4, CYCLE=16, WIDTH = 33)
(
	 input clk,
	 input rst,
    input signed [WIDTH-1:0] a_r,
    input signed [WIDTH-1:0] a_i,
    output reg signed[WIDTH+LOG_CYCLE-1:0] out_r,
    output reg signed[WIDTH+LOG_CYCLE-1:0] out_i
    );
	 
	 reg [LOG_CYCLE-1:0] count;
	 
	 always @(posedge clk or negedge rst)
		if(!rst)
			count <= 0;
		else if (count == CYCLE-1)
			count <= 0;
		else
			count <= count + 1;
			
	always @(posedge clk)
		if(count == 0)
		begin
			out_r <= a_r;
			out_i <= a_i;
		end
		else
		begin
			out_r <= out_r + a_r;
			out_i <= out_i + a_i;
		end
	 
endmodule
